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178
lab15/ALU-2_Markou.circ
Normal file
178
lab15/ALU-2_Markou.circ
Normal file
@@ -0,0 +1,178 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project source="2.7.1" version="1.0">
|
||||
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
|
||||
<lib desc="#Wiring" name="0">
|
||||
<tool name="Constant">
|
||||
<a name="value" val="0x0"/>
|
||||
</tool>
|
||||
</lib>
|
||||
<lib desc="#Gates" name="1"/>
|
||||
<lib desc="#Plexers" name="2"/>
|
||||
<lib desc="#Arithmetic" name="3"/>
|
||||
<lib desc="#Memory" name="4">
|
||||
<tool name="ROM">
|
||||
<a name="contents">addr/data: 8 8
|
||||
0
|
||||
</a>
|
||||
</tool>
|
||||
</lib>
|
||||
<lib desc="#I/O" name="5"/>
|
||||
<lib desc="#Base" name="6">
|
||||
<tool name="Text Tool">
|
||||
<a name="text" val=""/>
|
||||
<a name="font" val="SansSerif plain 12"/>
|
||||
<a name="halign" val="center"/>
|
||||
<a name="valign" val="base"/>
|
||||
</tool>
|
||||
</lib>
|
||||
<lib desc="file#AND8bit.circ" name="7"/>
|
||||
<lib desc="file#or8bit.circ" name="8"/>
|
||||
<lib desc="file#AdderSubtractor.circ" name="9"/>
|
||||
<main name="ALU"/>
|
||||
<options>
|
||||
<a name="gateUndefined" val="ignore"/>
|
||||
<a name="simlimit" val="1000"/>
|
||||
<a name="simrand" val="0"/>
|
||||
</options>
|
||||
<mappings>
|
||||
<tool lib="6" map="Button2" name="Menu Tool"/>
|
||||
<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
|
||||
<tool lib="6" map="Button3" name="Menu Tool"/>
|
||||
</mappings>
|
||||
<toolbar>
|
||||
<tool lib="6" name="Poke Tool"/>
|
||||
<tool lib="6" name="Edit Tool"/>
|
||||
<tool lib="6" name="Text Tool">
|
||||
<a name="text" val=""/>
|
||||
<a name="font" val="SansSerif plain 12"/>
|
||||
<a name="halign" val="center"/>
|
||||
<a name="valign" val="base"/>
|
||||
</tool>
|
||||
<sep/>
|
||||
<tool lib="0" name="Pin">
|
||||
<a name="width" val="8"/>
|
||||
<a name="tristate" val="false"/>
|
||||
</tool>
|
||||
<tool lib="0" name="Pin">
|
||||
<a name="facing" val="west"/>
|
||||
<a name="output" val="true"/>
|
||||
<a name="labelloc" val="east"/>
|
||||
</tool>
|
||||
<tool lib="1" name="NOT Gate"/>
|
||||
<tool lib="1" name="AND Gate"/>
|
||||
<tool lib="1" name="OR Gate"/>
|
||||
</toolbar>
|
||||
<circuit name="ALU">
|
||||
<a name="circuit" val="ALU"/>
|
||||
<a name="clabel" val="ALU"/>
|
||||
<a name="clabelup" val="north"/>
|
||||
<a name="clabelfont" val="SansSerif plain 12"/>
|
||||
<appear>
|
||||
<polyline fill="none" points="170,60 170,121" stroke="#000000" stroke-width="2"/>
|
||||
<polyline fill="none" points="152,158 170,122" stroke="#000000" stroke-width="2"/>
|
||||
<polyline fill="none" points="119,159 151,159" stroke="#000000" stroke-width="2"/>
|
||||
<polyline fill="none" points="120,121 119,157" stroke="#000000" stroke-width="2"/>
|
||||
<polyline fill="none" points="120,31 120,67" stroke="#000000" stroke-width="2"/>
|
||||
<path d="M121,68 Q146,90 120,120" fill="none" stroke="#000000" stroke-width="2"/>
|
||||
<polyline fill="none" points="121,30 150,30" stroke="#000000" stroke-width="2"/>
|
||||
<polyline fill="none" points="170,60 151,31" stroke="#000000" stroke-width="2"/>
|
||||
<circ-port height="8" pin="110,80" width="8" x="116" y="46"/>
|
||||
<circ-port height="8" pin="110,350" width="8" x="116" y="136"/>
|
||||
<circ-port height="10" pin="590,200" width="10" x="165" y="85"/>
|
||||
<circ-port height="8" pin="530,330" width="8" x="136" y="26"/>
|
||||
<circ-anchor facing="east" height="6" width="6" x="147" y="57"/>
|
||||
</appear>
|
||||
<wire from="(130,200)" to="(220,200)"/>
|
||||
<wire from="(130,200)" to="(130,290)"/>
|
||||
<wire from="(140,310)" to="(140,350)"/>
|
||||
<wire from="(490,210)" to="(490,260)"/>
|
||||
<wire from="(490,190)" to="(510,190)"/>
|
||||
<wire from="(140,130)" to="(140,220)"/>
|
||||
<wire from="(110,350)" to="(140,350)"/>
|
||||
<wire from="(300,170)" to="(430,170)"/>
|
||||
<wire from="(520,220)" to="(520,280)"/>
|
||||
<wire from="(440,250)" to="(440,280)"/>
|
||||
<wire from="(130,80)" to="(130,110)"/>
|
||||
<wire from="(310,260)" to="(310,280)"/>
|
||||
<wire from="(240,250)" to="(440,250)"/>
|
||||
<wire from="(130,110)" to="(220,110)"/>
|
||||
<wire from="(140,310)" to="(220,310)"/>
|
||||
<wire from="(300,170)" to="(300,210)"/>
|
||||
<wire from="(130,290)" to="(220,290)"/>
|
||||
<wire from="(140,130)" to="(220,130)"/>
|
||||
<wire from="(300,150)" to="(430,150)"/>
|
||||
<wire from="(440,180)" to="(440,250)"/>
|
||||
<wire from="(260,210)" to="(300,210)"/>
|
||||
<wire from="(140,220)" to="(220,220)"/>
|
||||
<wire from="(140,220)" to="(140,310)"/>
|
||||
<wire from="(490,210)" to="(510,210)"/>
|
||||
<wire from="(460,160)" to="(490,160)"/>
|
||||
<wire from="(540,200)" to="(590,200)"/>
|
||||
<wire from="(130,110)" to="(130,200)"/>
|
||||
<wire from="(260,120)" to="(300,120)"/>
|
||||
<wire from="(310,260)" to="(490,260)"/>
|
||||
<wire from="(110,80)" to="(130,80)"/>
|
||||
<wire from="(260,280)" to="(310,280)"/>
|
||||
<wire from="(530,300)" to="(530,330)"/>
|
||||
<wire from="(300,120)" to="(300,150)"/>
|
||||
<wire from="(240,250)" to="(240,270)"/>
|
||||
<wire from="(440,280)" to="(510,280)"/>
|
||||
<wire from="(490,160)" to="(490,190)"/>
|
||||
<comp lib="0" loc="(590,200)" name="Pin">
|
||||
<a name="facing" val="west"/>
|
||||
<a name="output" val="true"/>
|
||||
<a name="width" val="8"/>
|
||||
<a name="labelloc" val="east"/>
|
||||
</comp>
|
||||
<comp lib="6" loc="(464,397)" name="Text">
|
||||
<a name="text" val="11 -"/>
|
||||
</comp>
|
||||
<comp lib="9" loc="(240,280)" name="EightBitAdderSubtractor"/>
|
||||
<comp lib="2" loc="(460,160)" name="Multiplexer">
|
||||
<a name="width" val="8"/>
|
||||
<a name="enable" val="false"/>
|
||||
</comp>
|
||||
<comp lib="6" loc="(597,291)" name="Text">
|
||||
<a name="text" val="reverse the bit location"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(110,80)" name="Pin">
|
||||
<a name="width" val="8"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="a"/>
|
||||
</comp>
|
||||
<comp lib="2" loc="(540,200)" name="Multiplexer">
|
||||
<a name="width" val="8"/>
|
||||
<a name="enable" val="false"/>
|
||||
</comp>
|
||||
<comp lib="6" loc="(471,356)" name="Text">
|
||||
<a name="text" val="01 OR"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(530,300)" name="Splitter">
|
||||
<a name="facing" val="north"/>
|
||||
<a name="bit0" val="1"/>
|
||||
<a name="bit1" val="0"/>
|
||||
</comp>
|
||||
<comp lib="6" loc="(294,39)" name="Text">
|
||||
<a name="text" val="Full 8-bit ALU"/>
|
||||
<a name="font" val="SansSerif bold 24"/>
|
||||
</comp>
|
||||
<comp lib="6" loc="(466,375)" name="Text">
|
||||
<a name="text" val="10 +"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(530,330)" name="Pin">
|
||||
<a name="facing" val="north"/>
|
||||
<a name="width" val="2"/>
|
||||
<a name="tristate" val="false"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(110,350)" name="Pin">
|
||||
<a name="width" val="8"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="b"/>
|
||||
</comp>
|
||||
<comp lib="8" loc="(240,200)" name="OR8bit"/>
|
||||
<comp lib="6" loc="(475,338)" name="Text">
|
||||
<a name="text" val="00 AND"/>
|
||||
</comp>
|
||||
<comp lib="7" loc="(240,110)" name="AND8bit"/>
|
||||
</circuit>
|
||||
</project>
|
||||
109
lab15/ALU-Test_CalebFontenot.circ
Normal file
109
lab15/ALU-Test_CalebFontenot.circ
Normal file
@@ -0,0 +1,109 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project source="2.7.1" version="1.0">
|
||||
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
|
||||
|
||||
<lib desc="#Wiring" name="0">
|
||||
<tool name="Splitter">
|
||||
<a name="facing" val="north"/>
|
||||
<a name="fanout" val="8"/>
|
||||
<a name="incoming" val="8"/>
|
||||
<a name="appear" val="legacy"/>
|
||||
</tool>
|
||||
<tool name="Pin">
|
||||
<a name="facing" val="south"/>
|
||||
</tool>
|
||||
<tool name="Constant">
|
||||
<a name="value" val="0x0"/>
|
||||
</tool>
|
||||
</lib>
|
||||
<lib desc="#Gates" name="1"/>
|
||||
<lib desc="#Plexers" name="2"/>
|
||||
<lib desc="#Arithmetic" name="3"/>
|
||||
<lib desc="#Memory" name="4">
|
||||
<tool name="ROM">
|
||||
<a name="contents">addr/data: 8 8
|
||||
0
|
||||
</a>
|
||||
</tool>
|
||||
</lib>
|
||||
<lib desc="#I/O" name="5"/>
|
||||
<lib desc="#Base" name="6">
|
||||
<tool name="Text Tool">
|
||||
<a name="text" val=""/>
|
||||
<a name="font" val="SansSerif plain 12"/>
|
||||
<a name="halign" val="center"/>
|
||||
<a name="valign" val="base"/>
|
||||
</tool>
|
||||
<tool name="Text">
|
||||
<a name="text" val="a"/>
|
||||
</tool>
|
||||
</lib>
|
||||
<lib desc="file#/media/DataEXT4/Documents/Logisim/lab15/ALU_CalebFontenot.circ" name="7"/>
|
||||
<main name="main"/>
|
||||
<options>
|
||||
<a name="gateUndefined" val="ignore"/>
|
||||
<a name="simlimit" val="1000"/>
|
||||
<a name="simrand" val="0"/>
|
||||
</options>
|
||||
<mappings>
|
||||
<tool lib="6" map="Button2" name="Menu Tool"/>
|
||||
<tool lib="6" map="Button3" name="Menu Tool"/>
|
||||
<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
|
||||
</mappings>
|
||||
<toolbar>
|
||||
<tool lib="6" name="Poke Tool"/>
|
||||
<tool lib="6" name="Edit Tool"/>
|
||||
<tool lib="6" name="Text Tool">
|
||||
<a name="text" val=""/>
|
||||
<a name="font" val="SansSerif plain 12"/>
|
||||
<a name="halign" val="center"/>
|
||||
<a name="valign" val="base"/>
|
||||
</tool>
|
||||
<sep/>
|
||||
<tool lib="0" name="Pin">
|
||||
<a name="tristate" val="false"/>
|
||||
</tool>
|
||||
<tool lib="0" name="Pin">
|
||||
<a name="facing" val="west"/>
|
||||
<a name="output" val="true"/>
|
||||
<a name="labelloc" val="east"/>
|
||||
</tool>
|
||||
<tool lib="1" name="NOT Gate"/>
|
||||
<tool lib="1" name="AND Gate"/>
|
||||
<tool lib="1" name="OR Gate"/>
|
||||
</toolbar>
|
||||
<circuit name="main">
|
||||
<a name="circuit" val="main"/>
|
||||
<a name="clabel" val=""/>
|
||||
<a name="clabelup" val="east"/>
|
||||
<a name="clabelfont" val="SansSerif plain 12"/>
|
||||
<wire from="(220,210)" to="(300,210)"/>
|
||||
<wire from="(110,170)" to="(170,170)"/>
|
||||
<wire from="(110,260)" to="(170,260)"/>
|
||||
<wire from="(190,110)" to="(190,150)"/>
|
||||
<comp lib="0" loc="(300,210)" name="Pin">
|
||||
<a name="facing" val="west"/>
|
||||
<a name="output" val="true"/>
|
||||
<a name="width" val="8"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="labelloc" val="east"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(190,110)" name="Pin">
|
||||
<a name="facing" val="south"/>
|
||||
<a name="width" val="2"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="ALU Control"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(110,260)" name="Pin">
|
||||
<a name="width" val="8"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="b"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(110,170)" name="Pin">
|
||||
<a name="width" val="8"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="a"/>
|
||||
</comp>
|
||||
<comp lib="7" loc="(190,170)" name="ALU"/>
|
||||
</circuit>
|
||||
</project>
|
||||
183
lab15/ALU_CalebFontenot.circ
Normal file
183
lab15/ALU_CalebFontenot.circ
Normal file
@@ -0,0 +1,183 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project source="2.7.1" version="1.0">
|
||||
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
|
||||
|
||||
<lib desc="#Wiring" name="0">
|
||||
<tool name="Splitter">
|
||||
<a name="facing" val="north"/>
|
||||
<a name="fanout" val="8"/>
|
||||
<a name="incoming" val="8"/>
|
||||
<a name="appear" val="legacy"/>
|
||||
</tool>
|
||||
<tool name="Pin">
|
||||
<a name="facing" val="south"/>
|
||||
</tool>
|
||||
<tool name="Constant">
|
||||
<a name="value" val="0x0"/>
|
||||
</tool>
|
||||
</lib>
|
||||
<lib desc="#Gates" name="1"/>
|
||||
<lib desc="#Plexers" name="2"/>
|
||||
<lib desc="#Arithmetic" name="3"/>
|
||||
<lib desc="#Memory" name="4">
|
||||
<tool name="ROM">
|
||||
<a name="contents">addr/data: 8 8
|
||||
0
|
||||
</a>
|
||||
</tool>
|
||||
</lib>
|
||||
<lib desc="#I/O" name="5"/>
|
||||
<lib desc="#Base" name="6">
|
||||
<tool name="Text Tool">
|
||||
<a name="text" val=""/>
|
||||
<a name="font" val="SansSerif plain 12"/>
|
||||
<a name="halign" val="center"/>
|
||||
<a name="valign" val="base"/>
|
||||
</tool>
|
||||
<tool name="Text">
|
||||
<a name="text" val="a"/>
|
||||
</tool>
|
||||
</lib>
|
||||
<lib desc="file#/media/DataEXT4/Documents/Logisim/lab14/AdderSubtractor.circ" name="7"/>
|
||||
<lib desc="file#../AND8bit.circ" name="8"/>
|
||||
<lib desc="file#../OR8bit.circ" name="9"/>
|
||||
<lib desc="file#../AdderSubtractor_Markou.circ" name="10"/>
|
||||
<main name="ALU"/>
|
||||
<options>
|
||||
<a name="gateUndefined" val="ignore"/>
|
||||
<a name="simlimit" val="1000"/>
|
||||
<a name="simrand" val="0"/>
|
||||
</options>
|
||||
<mappings>
|
||||
<tool lib="6" map="Button2" name="Menu Tool"/>
|
||||
<tool lib="6" map="Button3" name="Menu Tool"/>
|
||||
<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
|
||||
</mappings>
|
||||
<toolbar>
|
||||
<tool lib="6" name="Poke Tool"/>
|
||||
<tool lib="6" name="Edit Tool"/>
|
||||
<tool lib="6" name="Text Tool">
|
||||
<a name="text" val=""/>
|
||||
<a name="font" val="SansSerif plain 12"/>
|
||||
<a name="halign" val="center"/>
|
||||
<a name="valign" val="base"/>
|
||||
</tool>
|
||||
<sep/>
|
||||
<tool lib="0" name="Pin">
|
||||
<a name="tristate" val="false"/>
|
||||
</tool>
|
||||
<tool lib="0" name="Pin">
|
||||
<a name="facing" val="west"/>
|
||||
<a name="output" val="true"/>
|
||||
<a name="labelloc" val="east"/>
|
||||
</tool>
|
||||
<tool lib="1" name="NOT Gate"/>
|
||||
<tool lib="1" name="AND Gate"/>
|
||||
<tool lib="1" name="OR Gate"/>
|
||||
</toolbar>
|
||||
<circuit name="ALU">
|
||||
<a name="circuit" val="ALU"/>
|
||||
<a name="clabel" val="ALU"/>
|
||||
<a name="clabelup" val="east"/>
|
||||
<a name="clabelfont" val="SansSerif plain 12"/>
|
||||
<appear>
|
||||
<path d="M50,100 Q70,75 50,50" fill="none" stroke="#000000"/>
|
||||
<polyline fill="none" points="50,50 50,10" stroke="#000000"/>
|
||||
<polyline fill="none" points="50,10 81,10" stroke="#000000"/>
|
||||
<polyline fill="none" points="100,50 100,100" stroke="#000000"/>
|
||||
<polyline fill="none" points="81,9 100,49" stroke="#000000"/>
|
||||
<polyline fill="none" points="100,101 80,130" stroke="#000000"/>
|
||||
<polyline fill="none" points="81,130 49,130" stroke="#000000"/>
|
||||
<polyline fill="none" points="50,100 50,130" stroke="#000000"/>
|
||||
<circ-port height="8" pin="120,140" width="8" x="46" y="26"/>
|
||||
<circ-port height="8" pin="130,410" width="8" x="46" y="116"/>
|
||||
<circ-port height="10" pin="630,230" width="10" x="95" y="65"/>
|
||||
<circ-port height="8" pin="510,460" width="8" x="66" y="6"/>
|
||||
<circ-anchor facing="east" height="6" width="6" x="67" y="27"/>
|
||||
</appear>
|
||||
<wire from="(190,160)" to="(190,290)"/>
|
||||
<wire from="(210,140)" to="(210,270)"/>
|
||||
<wire from="(400,170)" to="(460,170)"/>
|
||||
<wire from="(470,340)" to="(530,340)"/>
|
||||
<wire from="(130,410)" to="(190,410)"/>
|
||||
<wire from="(580,230)" to="(630,230)"/>
|
||||
<wire from="(450,240)" to="(450,380)"/>
|
||||
<wire from="(510,450)" to="(510,460)"/>
|
||||
<wire from="(530,340)" to="(530,370)"/>
|
||||
<wire from="(360,340)" to="(470,340)"/>
|
||||
<wire from="(450,240)" to="(550,240)"/>
|
||||
<wire from="(360,340)" to="(360,370)"/>
|
||||
<wire from="(510,450)" to="(550,450)"/>
|
||||
<wire from="(540,310)" to="(560,310)"/>
|
||||
<wire from="(490,160)" to="(520,160)"/>
|
||||
<wire from="(520,220)" to="(550,220)"/>
|
||||
<wire from="(120,140)" to="(210,140)"/>
|
||||
<wire from="(470,180)" to="(470,340)"/>
|
||||
<wire from="(400,170)" to="(400,280)"/>
|
||||
<wire from="(190,410)" to="(340,410)"/>
|
||||
<wire from="(190,290)" to="(340,290)"/>
|
||||
<wire from="(190,160)" to="(340,160)"/>
|
||||
<wire from="(380,280)" to="(400,280)"/>
|
||||
<wire from="(550,390)" to="(550,450)"/>
|
||||
<wire from="(540,310)" to="(540,370)"/>
|
||||
<wire from="(560,250)" to="(560,310)"/>
|
||||
<wire from="(380,150)" to="(460,150)"/>
|
||||
<wire from="(190,290)" to="(190,410)"/>
|
||||
<wire from="(210,270)" to="(210,390)"/>
|
||||
<wire from="(520,160)" to="(520,220)"/>
|
||||
<wire from="(210,270)" to="(340,270)"/>
|
||||
<wire from="(210,140)" to="(340,140)"/>
|
||||
<wire from="(210,390)" to="(340,390)"/>
|
||||
<wire from="(380,380)" to="(450,380)"/>
|
||||
<comp lib="0" loc="(130,410)" name="Pin">
|
||||
<a name="width" val="8"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="b"/>
|
||||
</comp>
|
||||
<comp lib="8" loc="(360,140)" name="AND8bit"/>
|
||||
<comp lib="0" loc="(120,140)" name="Pin">
|
||||
<a name="width" val="8"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="a"/>
|
||||
</comp>
|
||||
<comp lib="6" loc="(451,492)" name="Text">
|
||||
<a name="text" val="11 -"/>
|
||||
</comp>
|
||||
<comp lib="9" loc="(360,270)" name="OR8bit"/>
|
||||
<comp lib="2" loc="(580,230)" name="Multiplexer">
|
||||
<a name="width" val="8"/>
|
||||
<a name="enable" val="false"/>
|
||||
</comp>
|
||||
<comp lib="6" loc="(451,478)" name="Text">
|
||||
<a name="text" val="10 +"/>
|
||||
</comp>
|
||||
<comp lib="2" loc="(490,160)" name="Multiplexer">
|
||||
<a name="width" val="8"/>
|
||||
<a name="enable" val="false"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(550,390)" name="Splitter">
|
||||
<a name="facing" val="north"/>
|
||||
<a name="bit0" val="1"/>
|
||||
<a name="bit1" val="0"/>
|
||||
</comp>
|
||||
<comp lib="10" loc="(360,380)" name="EightBitAdderSubtractor"/>
|
||||
<comp lib="6" loc="(461,447)" name="Text">
|
||||
<a name="text" val="00 AND"/>
|
||||
</comp>
|
||||
<comp lib="6" loc="(457,463)" name="Text">
|
||||
<a name="text" val="01 OR"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(630,230)" name="Pin">
|
||||
<a name="facing" val="west"/>
|
||||
<a name="output" val="true"/>
|
||||
<a name="width" val="8"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="labelloc" val="east"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(510,460)" name="Pin">
|
||||
<a name="facing" val="north"/>
|
||||
<a name="width" val="2"/>
|
||||
<a name="tristate" val="false"/>
|
||||
</comp>
|
||||
</circuit>
|
||||
</project>
|
||||
BIN
lab15/labALU-1.pdf
Normal file
BIN
lab15/labALU-1.pdf
Normal file
Binary file not shown.
BIN
lab15/one+five.png
Normal file
BIN
lab15/one+five.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 2.7 KiB |
BIN
lab15/one-five.png
Normal file
BIN
lab15/one-five.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 2.6 KiB |
BIN
lab15/oneANDfive.png
Normal file
BIN
lab15/oneANDfive.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 2.6 KiB |
BIN
lab15/oneORfive.png
Normal file
BIN
lab15/oneORfive.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 2.7 KiB |
Reference in New Issue
Block a user