From b5f771ec70858cbbc29f5c3fac6aa8dd3abe0e8e Mon Sep 17 00:00:00 2001
From: Caleb Fontenot <foley2431@gmail.com>
Date: Wed, 12 Oct 2022 09:04:30 -0500
Subject: [PATCH] add lab19

---
 lab19/CPU_CalebFontenot.circ        | 437 ++++++++++++++--------------
 lab19/cpumemSubtract.txt            |   2 +-
 {lab17 => lab19}/labCPUcomplete.pdf | Bin
 lab19/minus10cpu.png                | Bin 0 -> 21321 bytes
 4 files changed, 223 insertions(+), 216 deletions(-)
 rename {lab17 => lab19}/labCPUcomplete.pdf (100%)
 create mode 100644 lab19/minus10cpu.png

diff --git a/lab19/CPU_CalebFontenot.circ b/lab19/CPU_CalebFontenot.circ
index 757293e..b445815 100644
--- a/lab19/CPU_CalebFontenot.circ
+++ b/lab19/CPU_CalebFontenot.circ
@@ -154,11 +154,14 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
     <wire from="(730,530)" to="(850,530)"/>
     <wire from="(620,640)" to="(620,650)"/>
     <wire from="(520,60)" to="(520,70)"/>
+    <wire from="(620,710)" to="(680,710)"/>
     <wire from="(290,550)" to="(290,560)"/>
     <wire from="(420,340)" to="(540,340)"/>
     <wire from="(100,520)" to="(150,520)"/>
     <wire from="(100,60)" to="(100,460)"/>
     <wire from="(340,560)" to="(340,580)"/>
+    <wire from="(680,710)" to="(720,710)"/>
+    <wire from="(680,670)" to="(720,670)"/>
     <wire from="(590,160)" to="(590,250)"/>
     <wire from="(690,550)" to="(690,580)"/>
     <wire from="(520,580)" to="(520,600)"/>
@@ -200,6 +203,7 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
     <wire from="(370,360)" to="(370,390)"/>
     <wire from="(610,520)" to="(610,540)"/>
     <wire from="(730,160)" to="(730,180)"/>
+    <wire from="(680,670)" to="(680,710)"/>
     <wire from="(730,400)" to="(730,440)"/>
     <wire from="(500,830)" to="(530,830)"/>
     <wire from="(710,530)" to="(730,530)"/>
@@ -217,25 +221,114 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
     <wire from="(730,160)" to="(740,160)"/>
     <wire from="(730,400)" to="(740,400)"/>
     <wire from="(640,350)" to="(650,350)"/>
-    <comp lib="0" loc="(730,380)" name="Pin">
+    <comp lib="0" loc="(640,350)" name="Tunnel">
       <a name="facing" val="south"/>
+      <a name="width" val="2"/>
+      <a name="label" val="dregsel"/>
+    </comp>
+    <comp lib="0" loc="(520,510)" name="Tunnel">
+      <a name="facing" val="east"/>
+      <a name="width" val="2"/>
+      <a name="label" val="regsel"/>
+    </comp>
+    <comp lib="0" loc="(940,480)" name="Pin">
+      <a name="facing" val="west"/>
       <a name="output" val="true"/>
       <a name="width" val="8"/>
-      <a name="labelloc" val="east"/>
+      <a name="tristate" val="false"/>
+      <a name="label" val="result"/>
+      <a name="labelloc" val="north"/>
     </comp>
-    <comp lib="0" loc="(620,180)" name="Tunnel">
-      <a name="label" val="pcsel"/>
+    <comp lib="0" loc="(370,390)" name="Clock">
+      <a name="facing" val="north"/>
+    </comp>
+    <comp lib="0" loc="(750,450)" name="Tunnel">
+      <a name="width" val="8"/>
+      <a name="label" val="r0"/>
+    </comp>
+    <comp lib="8" loc="(870,440)" name="ALU"/>
+    <comp lib="0" loc="(570,660)" name="Tunnel">
+      <a name="label" val="imload"/>
+    </comp>
+    <comp lib="0" loc="(980,90)" name="Tunnel">
+      <a name="width" val="8"/>
+      <a name="label" val="r0"/>
+    </comp>
+    <comp lib="4" loc="(390,340)" name="Register"/>
+    <comp lib="0" loc="(470,80)" name="Tunnel">
+      <a name="width" val="8"/>
+      <a name="label" val="dbus"/>
+    </comp>
+    <comp lib="0" loc="(690,350)" name="Tunnel">
+      <a name="facing" val="south"/>
+      <a name="width" val="2"/>
+      <a name="label" val="sregsel"/>
+    </comp>
+    <comp lib="0" loc="(590,540)" name="Tunnel">
+      <a name="facing" val="east"/>
+      <a name="label" val="dwrite"/>
     </comp>
     <comp lib="0" loc="(660,790)" name="Tunnel">
       <a name="label" val="pcload"/>
     </comp>
+    <comp lib="0" loc="(720,670)" name="Pin">
+      <a name="facing" val="west"/>
+      <a name="output" val="true"/>
+      <a name="width" val="2"/>
+      <a name="tristate" val="false"/>
+      <a name="labelloc" val="east"/>
+    </comp>
+    <comp lib="0" loc="(650,800)" name="Pin">
+      <a name="facing" val="north"/>
+      <a name="output" val="true"/>
+      <a name="labelloc" val="east"/>
+    </comp>
+    <comp lib="0" loc="(980,120)" name="Tunnel">
+      <a name="width" val="8"/>
+      <a name="label" val="r1"/>
+    </comp>
+    <comp lib="0" loc="(530,70)" name="Tunnel">
+      <a name="width" val="8"/>
+      <a name="label" val="sbus"/>
+    </comp>
+    <comp lib="0" loc="(520,440)" name="Tunnel">
+      <a name="facing" val="east"/>
+      <a name="width" val="8"/>
+      <a name="label" val="sbus"/>
+    </comp>
+    <comp lib="9" loc="(760,260)" name="programCounter">
+      <a name="facing" val="west"/>
+      <a name="labelloc" val="west"/>
+    </comp>
+    <comp lib="6" loc="(754,122)" name="Text">
+      <a name="text" val="PC"/>
+      <a name="font" val="SansSerif bold 20"/>
+    </comp>
+    <comp lib="4" loc="(260,460)" name="RAM">
+      <a name="bus" val="separate"/>
+    </comp>
+    <comp lib="0" loc="(740,570)" name="Tunnel">
+      <a name="width" val="8"/>
+      <a name="label" val="sbus"/>
+    </comp>
+    <comp lib="0" loc="(340,360)" name="Tunnel">
+      <a name="facing" val="north"/>
+      <a name="label" val="imload"/>
+    </comp>
+    <comp lib="0" loc="(750,500)" name="Tunnel">
+      <a name="width" val="8"/>
+      <a name="label" val="r2"/>
+    </comp>
+    <comp lib="0" loc="(530,860)" name="Tunnel">
+      <a name="width" val="2"/>
+      <a name="label" val="dregsel"/>
+    </comp>
     <comp lib="0" loc="(940,510)" name="Tunnel">
       <a name="width" val="8"/>
       <a name="label" val="ALU Result"/>
     </comp>
-    <comp lib="6" loc="(373,303)" name="Text">
-      <a name="text" val="ImmedR"/>
-      <a name="font" val="SansSerif bold 20"/>
+    <comp lib="0" loc="(750,180)" name="Clock">
+      <a name="facing" val="north"/>
     </comp>
     <comp lib="0" loc="(400,110)" name="Pin">
       <a name="output" val="true"/>
@@ -243,30 +336,57 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
       <a name="label" val="addrsel"/>
       <a name="labelloc" val="south"/>
     </comp>
-    <comp lib="0" loc="(520,440)" name="Tunnel">
-      <a name="facing" val="east"/>
-      <a name="width" val="8"/>
-      <a name="label" val="sbus"/>
+    <comp lib="6" loc="(52,399)" name="Text">
+      <a name="text" val="Memory Address"/>
     </comp>
-    <comp lib="0" loc="(750,180)" name="Clock">
+    <comp lib="0" loc="(950,90)" name="Pin">
+      <a name="output" val="true"/>
+      <a name="width" val="8"/>
+      <a name="tristate" val="false"/>
+      <a name="labelloc" val="east"/>
+    </comp>
+    <comp lib="0" loc="(340,580)" name="Clock">
       <a name="facing" val="north"/>
     </comp>
-    <comp lib="0" loc="(590,540)" name="Tunnel">
-      <a name="facing" val="east"/>
-      <a name="label" val="dwrite"/>
+    <comp lib="0" loc="(650,750)" name="Pin">
+      <a name="facing" val="south"/>
+      <a name="output" val="true"/>
+      <a name="labelloc" val="east"/>
     </comp>
-    <comp lib="0" loc="(740,570)" name="Tunnel">
+    <comp lib="0" loc="(660,760)" name="Tunnel">
+      <a name="label" val="pcsel"/>
+    </comp>
+    <comp lib="2" loc="(630,150)" name="Multiplexer">
       <a name="width" val="8"/>
-      <a name="label" val="sbus"/>
+      <a name="enable" val="false"/>
     </comp>
-    <comp lib="0" loc="(520,510)" name="Tunnel">
-      <a name="facing" val="east"/>
+    <comp lib="0" loc="(290,560)" name="Tunnel">
+      <a name="facing" val="north"/>
+      <a name="label" val="irload"/>
+    </comp>
+    <comp lib="0" loc="(370,770)" name="Pin">
+      <a name="output" val="true"/>
       <a name="width" val="2"/>
-      <a name="label" val="regsel"/>
+      <a name="labelloc" val="east"/>
     </comp>
-    <comp lib="0" loc="(980,150)" name="Tunnel">
+    <comp lib="4" loc="(770,150)" name="Register"/>
+    <comp lib="0" loc="(620,380)" name="Pin">
+      <a name="facing" val="south"/>
+      <a name="output" val="true"/>
       <a name="width" val="8"/>
-      <a name="label" val="r2"/>
+      <a name="labelloc" val="east"/>
+    </comp>
+    <comp lib="0" loc="(520,480)" name="Tunnel">
+      <a name="facing" val="east"/>
+      <a name="width" val="8"/>
+      <a name="label" val="ALU Result"/>
+    </comp>
+    <comp lib="6" loc="(133,56)" name="Text">
+      <a name="text" val="address bus"/>
+    </comp>
+    <comp lib="0" loc="(720,710)" name="Tunnel">
+      <a name="width" val="2"/>
+      <a name="label" val="aluop"/>
     </comp>
     <comp lib="0" loc="(950,150)" name="Pin">
       <a name="output" val="true"/>
@@ -280,141 +400,22 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
       <a name="width" val="8"/>
       <a name="labelloc" val="east"/>
     </comp>
+    <comp lib="0" loc="(570,740)" name="Tunnel">
+      <a name="label" val="readwrite"/>
+    </comp>
     <comp lib="0" loc="(620,650)" name="Tunnel">
       <a name="label" val="irload"/>
     </comp>
-    <comp lib="0" loc="(530,830)" name="Tunnel">
-      <a name="width" val="2"/>
-      <a name="label" val="sregsel"/>
-    </comp>
-    <comp lib="2" loc="(610,460)" name="Multiplexer">
-      <a name="select" val="2"/>
-      <a name="width" val="8"/>
-      <a name="enable" val="false"/>
-    </comp>
-    <comp lib="7" loc="(670,490)" name="Registers"/>
-    <comp lib="4" loc="(260,460)" name="RAM">
-      <a name="bus" val="separate"/>
-    </comp>
-    <comp lib="8" loc="(870,440)" name="ALU"/>
-    <comp lib="0" loc="(650,800)" name="Pin">
-      <a name="facing" val="north"/>
-      <a name="output" val="true"/>
-      <a name="labelloc" val="east"/>
-    </comp>
-    <comp lib="0" loc="(100,480)" name="Tunnel">
-      <a name="facing" val="east"/>
-      <a name="width" val="8"/>
-      <a name="label" val="dbus"/>
-    </comp>
-    <comp lib="2" loc="(410,60)" name="Multiplexer">
-      <a name="facing" val="west"/>
-      <a name="select" val="2"/>
-      <a name="width" val="8"/>
-      <a name="enable" val="false"/>
-    </comp>
-    <comp lib="0" loc="(340,580)" name="Clock">
-      <a name="facing" val="north"/>
-    </comp>
-    <comp lib="0" loc="(950,180)" name="Pin">
-      <a name="output" val="true"/>
-      <a name="width" val="8"/>
-      <a name="tristate" val="false"/>
-      <a name="labelloc" val="east"/>
-    </comp>
-    <comp lib="0" loc="(980,90)" name="Tunnel">
-      <a name="width" val="8"/>
-      <a name="label" val="r0"/>
-    </comp>
-    <comp lib="0" loc="(730,600)" name="Pin">
-      <a name="facing" val="north"/>
-      <a name="output" val="true"/>
-      <a name="width" val="8"/>
-      <a name="labelloc" val="east"/>
-    </comp>
     <comp lib="0" loc="(570,700)" name="Tunnel">
       <a name="label" val="dwrite"/>
     </comp>
-    <comp lib="0" loc="(620,680)" name="Tunnel">
-      <a name="width" val="2"/>
-      <a name="label" val="regsel"/>
-    </comp>
-    <comp lib="0" loc="(460,110)" name="Tunnel">
-      <a name="width" val="2"/>
-      <a name="label" val="addrsel"/>
-    </comp>
-    <comp lib="0" loc="(940,480)" name="Pin">
-      <a name="facing" val="west"/>
-      <a name="output" val="true"/>
+    <comp lib="0" loc="(750,520)" name="Tunnel">
       <a name="width" val="8"/>
-      <a name="tristate" val="false"/>
-      <a name="label" val="result"/>
-      <a name="labelloc" val="north"/>
+      <a name="label" val="r3"/>
     </comp>
-    <comp lib="6" loc="(754,122)" name="Text">
-      <a name="text" val="PC"/>
-      <a name="font" val="SansSerif bold 20"/>
-    </comp>
-    <comp lib="6" loc="(133,56)" name="Text">
-      <a name="text" val="address bus"/>
-    </comp>
-    <comp lib="0" loc="(190,510)" name="Clock">
-      <a name="facing" val="north"/>
-    </comp>
-    <comp lib="9" loc="(760,260)" name="programCounter">
-      <a name="facing" val="west"/>
-      <a name="labelloc" val="west"/>
-    </comp>
-    <comp lib="0" loc="(690,350)" name="Tunnel">
-      <a name="facing" val="south"/>
-      <a name="width" val="2"/>
-      <a name="label" val="sregsel"/>
-    </comp>
-    <comp lib="0" loc="(640,350)" name="Tunnel">
-      <a name="facing" val="south"/>
-      <a name="width" val="2"/>
-      <a name="label" val="dregsel"/>
-    </comp>
-    <comp lib="0" loc="(980,120)" name="Tunnel">
+    <comp lib="0" loc="(740,400)" name="Tunnel">
       <a name="width" val="8"/>
-      <a name="label" val="r1"/>
-    </comp>
-    <comp lib="0" loc="(340,360)" name="Tunnel">
-      <a name="facing" val="north"/>
-      <a name="label" val="imload"/>
-    </comp>
-    <comp lib="10" loc="(480,640)" name="logicNoChip"/>
-    <comp lib="0" loc="(750,500)" name="Tunnel">
-      <a name="width" val="8"/>
-      <a name="label" val="r2"/>
-    </comp>
-    <comp lib="0" loc="(290,560)" name="Tunnel">
-      <a name="facing" val="north"/>
-      <a name="label" val="imload"/>
-    </comp>
-    <comp lib="0" loc="(870,340)" name="Pin">
-      <a name="facing" val="south"/>
-      <a name="output" val="true"/>
-      <a name="width" val="2"/>
-      <a name="tristate" val="false"/>
-      <a name="label" val="ALU Operation"/>
-      <a name="labelloc" val="north"/>
-    </comp>
-    <comp lib="0" loc="(530,70)" name="Tunnel">
-      <a name="width" val="8"/>
-      <a name="label" val="sbus"/>
-    </comp>
-    <comp lib="0" loc="(720,180)" name="Tunnel">
-      <a name="facing" val="east"/>
-      <a name="label" val="pcload"/>
-    </comp>
-    <comp lib="2" loc="(630,150)" name="Multiplexer">
-      <a name="width" val="8"/>
-      <a name="enable" val="false"/>
-    </comp>
-    <comp lib="6" loc="(184,415)" name="Text">
-      <a name="text" val="RAM"/>
-      <a name="font" val="SansSerif bold 20"/>
+      <a name="label" val="dbus"/>
     </comp>
     <comp lib="0" loc="(240,40)" name="Pin">
       <a name="facing" val="south"/>
@@ -424,104 +425,110 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
       <a name="label" val="memory address"/>
       <a name="labelloc" val="north"/>
     </comp>
-    <comp lib="4" loc="(390,340)" name="Register"/>
-    <comp lib="4" loc="(770,150)" name="Register"/>
-    <comp lib="0" loc="(740,400)" name="Tunnel">
+    <comp lib="0" loc="(750,470)" name="Tunnel">
       <a name="width" val="8"/>
-      <a name="label" val="dbus"/>
+      <a name="label" val="r1"/>
+    </comp>
+    <comp lib="2" loc="(610,460)" name="Multiplexer">
+      <a name="select" val="2"/>
+      <a name="width" val="8"/>
+      <a name="enable" val="false"/>
+    </comp>
+    <comp lib="0" loc="(570,620)" name="Tunnel">
+      <a name="width" val="2"/>
+      <a name="label" val="addrsel"/>
+    </comp>
+    <comp lib="0" loc="(620,180)" name="Tunnel">
+      <a name="label" val="pcsel"/>
+    </comp>
+    <comp lib="4" loc="(360,540)" name="Register"/>
+    <comp lib="10" loc="(480,640)" name="logicNoChip"/>
+    <comp lib="0" loc="(980,150)" name="Tunnel">
+      <a name="width" val="8"/>
+      <a name="label" val="r2"/>
+    </comp>
+    <comp lib="0" loc="(730,600)" name="Pin">
+      <a name="facing" val="north"/>
+      <a name="output" val="true"/>
+      <a name="width" val="8"/>
+      <a name="labelloc" val="east"/>
+    </comp>
+    <comp lib="0" loc="(530,830)" name="Tunnel">
+      <a name="width" val="2"/>
+      <a name="label" val="sregsel"/>
+    </comp>
+    <comp lib="0" loc="(730,380)" name="Pin">
+      <a name="facing" val="south"/>
+      <a name="output" val="true"/>
+      <a name="width" val="8"/>
+      <a name="labelloc" val="east"/>
     </comp>
     <comp lib="6" loc="(754,290)" name="Text">
       <a name="text" val="PC Adder"/>
       <a name="font" val="SansSerif bold 18"/>
     </comp>
-    <comp lib="0" loc="(620,710)" name="Tunnel">
-      <a name="width" val="2"/>
-      <a name="label" val="aluop"/>
-    </comp>
-    <comp lib="0" loc="(910,360)" name="Tunnel">
-      <a name="width" val="2"/>
-      <a name="label" val="aloup"/>
-    </comp>
     <comp lib="0" loc="(980,180)" name="Tunnel">
       <a name="width" val="8"/>
       <a name="label" val="r3"/>
     </comp>
-    <comp lib="0" loc="(530,860)" name="Tunnel">
-      <a name="width" val="2"/>
-      <a name="label" val="dregsel"/>
-    </comp>
-    <comp lib="0" loc="(520,480)" name="Tunnel">
-      <a name="facing" val="east"/>
-      <a name="width" val="8"/>
-      <a name="label" val="ALU Result"/>
-    </comp>
     <comp lib="0" loc="(950,120)" name="Pin">
       <a name="output" val="true"/>
       <a name="width" val="8"/>
       <a name="tristate" val="false"/>
       <a name="labelloc" val="east"/>
     </comp>
+    <comp lib="2" loc="(410,60)" name="Multiplexer">
+      <a name="facing" val="west"/>
+      <a name="select" val="2"/>
+      <a name="width" val="8"/>
+      <a name="enable" val="false"/>
+    </comp>
+    <comp lib="0" loc="(190,510)" name="Clock">
+      <a name="facing" val="north"/>
+    </comp>
     <comp lib="0" loc="(100,520)" name="Tunnel">
       <a name="facing" val="east"/>
       <a name="label" val="readwrite"/>
     </comp>
-    <comp lib="0" loc="(950,90)" name="Pin">
+    <comp lib="0" loc="(100,480)" name="Tunnel">
+      <a name="facing" val="east"/>
+      <a name="width" val="8"/>
+      <a name="label" val="dbus"/>
+    </comp>
+    <comp lib="0" loc="(870,340)" name="Pin">
+      <a name="facing" val="south"/>
+      <a name="output" val="true"/>
+      <a name="width" val="2"/>
+      <a name="tristate" val="false"/>
+      <a name="label" val="ALU Operation"/>
+      <a name="labelloc" val="north"/>
+    </comp>
+    <comp lib="0" loc="(950,180)" name="Pin">
       <a name="output" val="true"/>
       <a name="width" val="8"/>
       <a name="tristate" val="false"/>
       <a name="labelloc" val="east"/>
     </comp>
-    <comp lib="0" loc="(660,760)" name="Tunnel">
-      <a name="label" val="pcsel"/>
+    <comp lib="0" loc="(620,680)" name="Tunnel">
+      <a name="width" val="2"/>
+      <a name="label" val="regsel"/>
     </comp>
-    <comp lib="0" loc="(470,80)" name="Tunnel">
-      <a name="width" val="8"/>
-      <a name="label" val="dbus"/>
+    <comp lib="0" loc="(910,360)" name="Tunnel">
+      <a name="width" val="2"/>
+      <a name="label" val="aluop"/>
     </comp>
-    <comp lib="0" loc="(750,470)" name="Tunnel">
-      <a name="width" val="8"/>
-      <a name="label" val="r1"/>
+    <comp lib="7" loc="(670,490)" name="Registers"/>
+    <comp lib="6" loc="(373,303)" name="Text">
+      <a name="text" val="ImmedR"/>
+      <a name="font" val="SansSerif bold 20"/>
     </comp>
-    <comp lib="6" loc="(52,399)" name="Text">
-      <a name="text" val="Memory Address"/>
+    <comp lib="0" loc="(720,180)" name="Tunnel">
+      <a name="facing" val="east"/>
+      <a name="label" val="pcload"/>
     </comp>
-    <comp lib="0" loc="(570,620)" name="Tunnel">
+    <comp lib="0" loc="(460,110)" name="Tunnel">
       <a name="width" val="2"/>
       <a name="label" val="addrsel"/>
     </comp>
-    <comp lib="4" loc="(360,540)" name="Register"/>
-    <comp lib="0" loc="(750,520)" name="Tunnel">
-      <a name="width" val="8"/>
-      <a name="label" val="r3"/>
-    </comp>
-    <comp lib="0" loc="(370,770)" name="Pin">
-      <a name="output" val="true"/>
-      <a name="width" val="2"/>
-      <a name="labelloc" val="east"/>
-    </comp>
-    <comp lib="0" loc="(570,740)" name="Tunnel">
-      <a name="label" val="readwrite"/>
-    </comp>
-    <comp lib="0" loc="(620,380)" name="Pin">
-      <a name="facing" val="south"/>
-      <a name="output" val="true"/>
-      <a name="width" val="8"/>
-      <a name="labelloc" val="east"/>
-    </comp>
-    <comp lib="0" loc="(650,750)" name="Pin">
-      <a name="facing" val="south"/>
-      <a name="output" val="true"/>
-      <a name="labelloc" val="east"/>
-    </comp>
-    <comp lib="0" loc="(570,660)" name="Tunnel">
-      <a name="label" val="imload"/>
-    </comp>
-    <comp lib="0" loc="(750,450)" name="Tunnel">
-      <a name="width" val="8"/>
-      <a name="label" val="r0"/>
-    </comp>
-    <comp lib="0" loc="(370,390)" name="Clock">
-      <a name="facing" val="north"/>
-    </comp>
   </circuit>
 </project>
diff --git a/lab19/cpumemSubtract.txt b/lab19/cpumemSubtract.txt
index 6351c10..1f269c3 100644
--- a/lab19/cpumemSubtract.txt
+++ b/lab19/cpumemSubtract.txt
@@ -1,4 +1,4 @@
 v2.0 raw
 e4 0 e0 80 48 88 d 36
-ec 1 33 ff 4 d4 40 ff
+ec 1 23 ff 4 d4 40 ff
 f 111*0 1 2 3 4
diff --git a/lab17/labCPUcomplete.pdf b/lab19/labCPUcomplete.pdf
similarity index 100%
rename from lab17/labCPUcomplete.pdf
rename to lab19/labCPUcomplete.pdf
diff --git a/lab19/minus10cpu.png b/lab19/minus10cpu.png
new file mode 100644
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