From 2b0acd36e19f27720b2740efbe68d0f7598ee5c5 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Sun, 14 Dec 2014 23:00:29 -0500
Subject: [PATCH] armemu: Fix UXTB16

Rotation bits are 10 and 11, not 9 and 10.
---
 src/core/arm/interpreter/armemu.cpp | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index ec40881f8..33ebc7986 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -6101,18 +6101,18 @@ L_stm_s_takeabort:
 
 			return 1;
 		}
-        case 0x6c:
-            if ((instr & 0xf03f0) == 0xf0070) { //uxtb16
-                u8 src1 = BITS(0, 3);
-                u8 tar = BITS(12, 15);
-                u32 base = state->Reg[src1];
-                u32 shamt = BITS(9,10)* 8;
-                u32 in = ((base << (32 - shamt)) | (base >> shamt));
-                state->Reg[tar] = in & 0x00FF00FF;
-                return 1;
-            } else
-                printf ("Unhandled v6 insn: uxtab16\n");
-            break;
+		case 0x6c:
+			if ((instr & 0xf03f0) == 0xf0070) { //uxtb16
+				u8 rm_idx = BITS(0, 3);
+				u8 rd_idx = BITS(12, 15);
+				u32 rm_val = state->Reg[rm_idx];
+				u32 rotation = BITS(10, 11) * 8;
+				u32 in = ((rm_val << (32 - rotation)) | (rm_val >> rotation));
+				state->Reg[rd_idx] = in & 0x00FF00FF;
+				return 1;
+			} else
+				printf ("Unhandled v6 insn: uxtab16\n");
+			break;
 		case 0x6e: {
 			ARMword Rm;
 			int ror = -1;