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Refactoring HOS folder structure (#771)

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* Refactoring HOS folder structure

Refactoring HOS folder structure:

- Added some subfolders when needed (Following structure decided in private).
- Added some `Types` folders when needed.
- Little cleanup here and there.
- Add services placeholders for every HOS services (close #766 and #753).

* Remove Types namespaces
This commit is contained in:
Ac_K
2019-09-19 02:45:11 +02:00
committed by jduncanator
parent 4af3101b22
commit a0720b5681
393 changed files with 2540 additions and 1299 deletions
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190
Ryujinx.HLE/HOS/Services/Nv/NvDrvServices/NvGpuGpu/NvGpuGpuIoctl.cs Normal file
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using ARMeilleure.Memory;
using Ryujinx.Common.Logging;
using System;
using System.Diagnostics;
namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvGpuGpu
{
class NvGpuGpuIoctl
{
private static Stopwatch _pTimer;
private static double _ticksToNs;
static NvGpuGpuIoctl()
{
_pTimer = new Stopwatch();
_pTimer.Start();
_ticksToNs = (1.0 / Stopwatch.Frequency) * 1_000_000_000;
}
public static int ProcessIoctl(ServiceCtx context, int cmd)
{
switch (cmd & 0xffff)
{
case 0x4701: return ZcullGetCtxSize (context);
case 0x4702: return ZcullGetInfo (context);
case 0x4703: return ZbcSetTable (context);
case 0x4705: return GetCharacteristics(context);
case 0x4706: return GetTpcMasks (context);
case 0x4714: return GetActiveSlotMask (context);
case 0x471c: return GetGpuTime (context);
}
throw new NotImplementedException(cmd.ToString("x8"));
}
private static int ZcullGetCtxSize(ServiceCtx context)
{
long outputPosition = context.Request.GetBufferType0x22().Position;
NvGpuGpuZcullGetCtxSize args = new NvGpuGpuZcullGetCtxSize
{
Size = 1
};
MemoryHelper.Write(context.Memory, outputPosition, args);
Logger.PrintStub(LogClass.ServiceNv);
return NvResult.Success;
}
private static int ZcullGetInfo(ServiceCtx context)
{
long outputPosition = context.Request.GetBufferType0x22().Position;
NvGpuGpuZcullGetInfo args = new NvGpuGpuZcullGetInfo
{
WidthAlignPixels = 0x20,
HeightAlignPixels = 0x20,
PixelSquaresByAliquots = 0x400,
AliquotTotal = 0x800,
RegionByteMultiplier = 0x20,
RegionHeaderSize = 0x20,
SubregionHeaderSize = 0xc0,
SubregionWidthAlignPixels = 0x20,
SubregionHeightAlignPixels = 0x40,
SubregionCount = 0x10
};
MemoryHelper.Write(context.Memory, outputPosition, args);
Logger.PrintStub(LogClass.ServiceNv);
return NvResult.Success;
}
private static int ZbcSetTable(ServiceCtx context)
{
long inputPosition = context.Request.GetBufferType0x21().Position;
long outputPosition = context.Request.GetBufferType0x22().Position;
Logger.PrintStub(LogClass.ServiceNv);
return NvResult.Success;
}
private static int GetCharacteristics(ServiceCtx context)
{
long inputPosition = context.Request.GetBufferType0x21().Position;
long outputPosition = context.Request.GetBufferType0x22().Position;
NvGpuGpuGetCharacteristics args = MemoryHelper.Read<NvGpuGpuGetCharacteristics>(context.Memory, inputPosition);
args.BufferSize = 0xa0;
args.Arch = 0x120;
args.Impl = 0xb;
args.Rev = 0xa1;
args.NumGpc = 0x1;
args.L2CacheSize = 0x40000;
args.OnBoardVideoMemorySize = 0x0;
args.NumTpcPerGpc = 0x2;
args.BusType = 0x20;
args.BigPageSize = 0x20000;
args.CompressionPageSize = 0x20000;
args.PdeCoverageBitCount = 0x1b;
args.AvailableBigPageSizes = 0x30000;
args.GpcMask = 0x1;
args.SmArchSmVersion = 0x503;
args.SmArchSpaVersion = 0x503;
args.SmArchWarpCount = 0x80;
args.GpuVaBitCount = 0x28;
args.Reserved = 0x0;
args.Flags = 0x55;
args.TwodClass = 0x902d;
args.ThreedClass = 0xb197;
args.ComputeClass = 0xb1c0;
args.GpfifoClass = 0xb06f;
args.InlineToMemoryClass = 0xa140;
args.DmaCopyClass = 0xb0b5;
args.MaxFbpsCount = 0x1;
args.FbpEnMask = 0x0;
args.MaxLtcPerFbp = 0x2;
args.MaxLtsPerLtc = 0x1;
args.MaxTexPerTpc = 0x0;
args.MaxGpcCount = 0x1;
args.RopL2EnMask0 = 0x21d70;
args.RopL2EnMask1 = 0x0;
args.ChipName = 0x6230326d67;
args.GrCompbitStoreBaseHw = 0x0;
MemoryHelper.Write(context.Memory, outputPosition, args);
return NvResult.Success;
}
private static int GetTpcMasks(ServiceCtx context)
{
long inputPosition = context.Request.GetBufferType0x21().Position;
long outputPosition = context.Request.GetBufferType0x22().Position;
NvGpuGpuGetTpcMasks args = MemoryHelper.Read<NvGpuGpuGetTpcMasks>(context.Memory, inputPosition);
if (args.MaskBufferSize != 0)
{
args.TpcMask = 3;
}
MemoryHelper.Write(context.Memory, outputPosition, args);
return NvResult.Success;
}
private static int GetActiveSlotMask(ServiceCtx context)
{
long outputPosition = context.Request.GetBufferType0x22().Position;
NvGpuGpuGetActiveSlotMask args = new NvGpuGpuGetActiveSlotMask
{
Slot = 0x07,
Mask = 0x01
};
MemoryHelper.Write(context.Memory, outputPosition, args);
Logger.PrintStub(LogClass.ServiceNv);
return NvResult.Success;
}
private static int GetGpuTime(ServiceCtx context)
{
long outputPosition = context.Request.GetBufferType0x22().Position;
context.Memory.WriteInt64(outputPosition, GetPTimerNanoSeconds());
return NvResult.Success;
}
private static long GetPTimerNanoSeconds()
{
double ticks = _pTimer.ElapsedTicks;
return (long)(ticks * _ticksToNs) & 0xff_ffff_ffff_ffff;
}
}
}

8
Ryujinx.HLE/HOS/Services/Nv/NvDrvServices/NvGpuGpu/Types/NvGpuGpuGetActiveSlotMask.cs Normal file
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namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvGpuGpu
{
struct NvGpuGpuGetActiveSlotMask
{
public int Slot;
public int Mask;
}
}

43
Ryujinx.HLE/HOS/Services/Nv/NvDrvServices/NvGpuGpu/Types/NvGpuGpuGetCharacteristics.cs Normal file
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namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvGpuGpu
{
struct NvGpuGpuGetCharacteristics
{
public long BufferSize;
public long BufferAddress;
public int Arch;
public int Impl;
public int Rev;
public int NumGpc;
public long L2CacheSize;
public long OnBoardVideoMemorySize;
public int NumTpcPerGpc;
public int BusType;
public int BigPageSize;
public int CompressionPageSize;
public int PdeCoverageBitCount;
public int AvailableBigPageSizes;
public int GpcMask;
public int SmArchSmVersion;
public int SmArchSpaVersion;
public int SmArchWarpCount;
public int GpuVaBitCount;
public int Reserved;
public long Flags;
public int TwodClass;
public int ThreedClass;
public int ComputeClass;
public int GpfifoClass;
public int InlineToMemoryClass;
public int DmaCopyClass;
public int MaxFbpsCount;
public int FbpEnMask;
public int MaxLtcPerFbp;
public int MaxLtsPerLtc;
public int MaxTexPerTpc;
public int MaxGpcCount;
public int RopL2EnMask0;
public int RopL2EnMask1;
public long ChipName;
public long GrCompbitStoreBaseHw;
}
}

11
Ryujinx.HLE/HOS/Services/Nv/NvDrvServices/NvGpuGpu/Types/NvGpuGpuGetTpcMasks.cs Normal file
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namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvGpuGpu
{
struct NvGpuGpuGetTpcMasks
{
public int MaskBufferSize;
public int Reserved;
public long MaskBufferAddress;
public int TpcMask;
public int Padding;
}
}

7
Ryujinx.HLE/HOS/Services/Nv/NvDrvServices/NvGpuGpu/Types/NvGpuGpuZcullGetCtxSize.cs Normal file
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namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvGpuGpu
{
struct NvGpuGpuZcullGetCtxSize
{
public int Size;
}
}

16
Ryujinx.HLE/HOS/Services/Nv/NvDrvServices/NvGpuGpu/Types/NvGpuGpuZcullGetInfo.cs Normal file
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namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvGpuGpu
{
struct NvGpuGpuZcullGetInfo
{
public int WidthAlignPixels;
public int HeightAlignPixels;
public int PixelSquaresByAliquots;
public int AliquotTotal;
public int RegionByteMultiplier;
public int RegionHeaderSize;
public int SubregionHeaderSize;
public int SubregionWidthAlignPixels;
public int SubregionHeightAlignPixels;
public int SubregionCount;
}
}