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	shader/arithmetic: Implement FCMP
Compares the third operand with zero, then selects between the first and second.
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		| @@ -1095,6 +1095,11 @@ union Instruction { | ||||
|         BitField<55, 1, u64> ftz; | ||||
|     } fset; | ||||
|  | ||||
|     union { | ||||
|         BitField<47, 1, u64> ftz; | ||||
|         BitField<48, 4, PredCondition> cond; | ||||
|     } fcmp; | ||||
|  | ||||
|     union { | ||||
|         BitField<49, 1, u64> bf; | ||||
|         BitField<35, 3, PredCondition> cond; | ||||
| @@ -1771,6 +1776,7 @@ public: | ||||
|         ICMP_R, | ||||
|         ICMP_CR, | ||||
|         ICMP_IMM, | ||||
|         FCMP_R, | ||||
|         MUFU,  // Multi-Function Operator | ||||
|         RRO_C, // Range Reduction Operator | ||||
|         RRO_R, | ||||
| @@ -2074,6 +2080,7 @@ private: | ||||
|             INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP2_R"), | ||||
|             INST("0111111-0-------", Id::HSETP2_IMM, Type::HalfSetPredicate, "HSETP2_IMM"), | ||||
|             INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"), | ||||
|             INST("010110111010----", Id::FCMP_R, Type::Arithmetic, "FCMP_R"), | ||||
|             INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), | ||||
|             INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), | ||||
|             INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"), | ||||
|   | ||||
| @@ -21,7 +21,7 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) { | ||||
|  | ||||
|     Node op_a = GetRegister(instr.gpr8); | ||||
|  | ||||
|     Node op_b = [&]() -> Node { | ||||
|     Node op_b = [&] { | ||||
|         if (instr.is_b_imm) { | ||||
|             return GetImmediate19(instr); | ||||
|         } else if (instr.is_b_gpr) { | ||||
| @@ -141,6 +141,15 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) { | ||||
|         SetRegister(bb, instr.gpr0, value); | ||||
|         break; | ||||
|     } | ||||
|     case OpCode::Id::FCMP_R: { | ||||
|         UNIMPLEMENTED_IF(instr.fcmp.ftz == 0); | ||||
|         Node op_c = GetRegister(instr.gpr39); | ||||
|         Node comp = GetPredicateComparisonFloat(instr.fcmp.cond, std::move(op_c), Immediate(0.0f)); | ||||
|         SetRegister( | ||||
|             bb, instr.gpr0, | ||||
|             Operation(OperationCode::Select, std::move(comp), std::move(op_a), std::move(op_b))); | ||||
|         break; | ||||
|     } | ||||
|     case OpCode::Id::RRO_C: | ||||
|     case OpCode::Id::RRO_R: | ||||
|     case OpCode::Id::RRO_IMM: { | ||||
|   | ||||
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