Merge pull request #1903 from heapo/fmul_postfactor
Implement postfactor multiplication/division for fmul instructions
This commit is contained in:
		| @@ -575,7 +575,7 @@ union Instruction { | |||||||
|  |  | ||||||
|     union { |     union { | ||||||
|         BitField<39, 2, u64> tab5cb8_2; |         BitField<39, 2, u64> tab5cb8_2; | ||||||
|         BitField<41, 3, u64> tab5c68_1; |         BitField<41, 3, u64> postfactor; | ||||||
|         BitField<44, 2, u64> tab5c68_0; |         BitField<44, 2, u64> tab5c68_0; | ||||||
|         BitField<48, 1, u64> negate_b; |         BitField<48, 1, u64> negate_b; | ||||||
|     } fmul; |     } fmul; | ||||||
|   | |||||||
| @@ -1867,9 +1867,6 @@ private: | |||||||
|                 UNIMPLEMENTED_IF_MSG(instr.fmul.tab5cb8_2 != 0, |                 UNIMPLEMENTED_IF_MSG(instr.fmul.tab5cb8_2 != 0, | ||||||
|                                      "FMUL tab5cb8_2({}) is not implemented", |                                      "FMUL tab5cb8_2({}) is not implemented", | ||||||
|                                      instr.fmul.tab5cb8_2.Value()); |                                      instr.fmul.tab5cb8_2.Value()); | ||||||
|                 UNIMPLEMENTED_IF_MSG(instr.fmul.tab5c68_1 != 0, |  | ||||||
|                                      "FMUL tab5cb8_1({}) is not implemented", |  | ||||||
|                                      instr.fmul.tab5c68_1.Value()); |  | ||||||
|                 UNIMPLEMENTED_IF_MSG( |                 UNIMPLEMENTED_IF_MSG( | ||||||
|                     instr.fmul.tab5c68_0 != 1, "FMUL tab5cb8_0({}) is not implemented", |                     instr.fmul.tab5c68_0 != 1, "FMUL tab5cb8_0({}) is not implemented", | ||||||
|                     instr.fmul.tab5c68_0 |                     instr.fmul.tab5c68_0 | ||||||
| @@ -1879,7 +1876,26 @@ private: | |||||||
|  |  | ||||||
|                 op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b); |                 op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b); | ||||||
|  |  | ||||||
|                 regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1, |                 std::string postfactor_op; | ||||||
|  |                 if (instr.fmul.postfactor != 0) { | ||||||
|  |                     s8 postfactor = static_cast<s8>(instr.fmul.postfactor); | ||||||
|  |  | ||||||
|  |                     // postfactor encoded as 3-bit 1's complement in instruction, | ||||||
|  |                     // interpreted with below logic. | ||||||
|  |                     if (postfactor >= 4) { | ||||||
|  |                         postfactor = 7 - postfactor; | ||||||
|  |                     } else { | ||||||
|  |                         postfactor = 0 - postfactor; | ||||||
|  |                     } | ||||||
|  |  | ||||||
|  |                     if (postfactor > 0) { | ||||||
|  |                         postfactor_op = " * " + std::to_string(1 << postfactor); | ||||||
|  |                     } else { | ||||||
|  |                         postfactor_op = " / " + std::to_string(1 << -postfactor); | ||||||
|  |                     } | ||||||
|  |                 } | ||||||
|  |  | ||||||
|  |                 regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b + postfactor_op, 1, 1, | ||||||
|                                         instr.alu.saturate_d, 0, true); |                                         instr.alu.saturate_d, 0, true); | ||||||
|                 break; |                 break; | ||||||
|             } |             } | ||||||
|   | |||||||
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